Power electronics based on wide-bandgap semiconductors: opportunities and challenges

The expansion of the electric vehicle market is driving the request for efficient and reliable power electronic systems for electric energy conversion and processing. The efficiency, size, and cost of a power system is strongly related to the performance of power semiconductor devices, where massive industrial investments and intense research efforts are being devoted to new wide bandgap (WBG) semiconductors, such as silicon carbide (SiC) and gallium nitride (GaN). The electrical and thermal properties of SiC and GaN enable the fabrication of semiconductor power devices with performance well beyond the limits of silicon. However, a massive migration of the power electronics industry towards WBG materials can be obtained only once the corresponding fabrication technology reaches a sufficient maturity and a competitive cost. In this paper, we present a perspective of power electronics based on WBG semiconductors, from fundamental material characteristics of SiC and GaN to their potential impacts on the power semiconductor device market. Some application cases are also presented, with specific benchmarks against a corresponding implementation realized with silicon devices, focusing on both achievable performance and system cost

Mixed Tunnel-FET/MOSFET Level Shifters: A New Proposal to Extend the Tunnel-FET Application Domain

In this paper, we identify the level shifter (LS) for voltage up-conversion from the ultralow-voltage regime as a key application domain of tunnel FETs (TFETs).We propose a mixed TFET\u2013MOSFET LS design methodology, which exploits the complementary characteristics of TFET and MOSFET devices. Simulation results show that the hybrid LS exhibits superior dynamic performance at the same static power consumption compared with the conventional MOSFET and pure TFET solutions. The advantage of the mixed design with respect to the conventional MOSFET approach is emphasized when lower voltage signals have to be up-converted, reaching an improvement of the energy-delay product up to three decades. When compared with the full MOSFET design, the mixed TFET\u2013MOSFET solution appears to be less sensitive toward threshold voltage variations in terms of dynamic figures of merit, at the expense of higher leakage variability. Similar results are obtained for four different LS topologies, thus indicating that the hybrid TFET\u2013MOSFET approach offers intrinsic advantages in the design of LS for voltage up-conversion from the ultralow-voltage regime compared with the conventional MOSFET and pure TFET solutions

Analog Vector-Matrix Multiplier Based on Programmable Current Mirrors for Neural Network Integrated Circuits

We propose a CMOS Analog Vector-Matrix Multiplier for Deep Neural Networks, implemented in a standard single-poly 180 nm CMOS technology. The learning weights are stored in analog floating-gate memory cells embedded in current mirrors implementing the multiplication operations. We experimentally verify the analog storage capability of designed single-poly floating-gate cells, the accuracy of the multiplying function of proposed tunable current mirrors, and the effective number of bits of the analog operation. We perform system-level simulations to show that an analog deep neural network based on the proposed vector-matrix multiplier can achieve an inference accuracy comparable to digital solutions with an energy efficiency of 26.4 TOPs/J, a layer latency close to 100 mu s and an intrinsically high degree of parallelism. Our proposed design has also a cost advantage, considering that it can be implemented in a standard single-poly CMOS process flow

Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits

In this work, a complementary InAs/Al0.05Ga0.95Sb tunnel field-effect-transistor (TFET) virtual technology platform is benchmarked against the projection to the CMOS FinFET 10-nm node, by means of device and basic circuit simulations. The comparison is performed in the ultralow voltage regime (below 500 mV), where the proposed III\u2013V TFETs feature ON-current levels comparable to scaled FinFETs, for the same low-operating-power OFF-current. Due to the asymmetrical n- and p-type I\u2013Vs, trends of noise margins and performances are investigated for different Wp/Wn ratios. Implications of the device threshold voltage variability, which turned out to be dramatic for steep slope TFETs, are also addressed

A 2-D-Material FET Verilog-A Model for Analog Neuromorphic Circuit Design

This work was supported in part by the European Project through European Research Council (ERC) Printable Electronic on Paper Through 2D Material based Inks (PEP2D) under Grant 770047, in part by Origami Electronics for three-dimensional integration of computational devices (ORIGENAL) under Grant 828901, and in part by Quantum Engineering for Machine Learning (QUEFORMAL) under Grant 829035. The work of Enrique G. Marin was supported in part by MCIN/AEI/10.13039/501100011033 under Project PID2020-116518GB-I00 and in part by FEDER/Junta de Andalucia under Project A-TIC-646-UGR20.We present a charge-based Verilog-A model for 2-D-material (2DM)-based field-effect transistors (FETs) with application in neuromorphic circuit design. The model combines the explicit solution of the drift-diffusion transport and electrostatics, including Fermi-Dirac statistics. The Ward-Dutton linear charge partitioning scheme is then employed for terminal charges and capacitance calculations. The model accurately predicts the electrical behavior of experimental MoS2 FETs, and it is applied to simulate neuromorphic-circuit building blocks, including a floating-gate (FG) current-mirror (CM) vector-matrix multi-plier (VMM), extracting the effective number of bits under different operation conditions.European Project through European Research Council (ERC) Printable Electronic on Paper Through 2D Material based Inks (PEP2D) 770047Origami Electronics for three-dimensional integration of computational devices (ORIGENAL) 828901Quantum Engineering for Machine Learning (QUEFORMAL) 829035MCIN/AEI PID2020-116518GB-I00FEDER/Junta de Andalucia A-TIC-646-UGR2

Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits

In this paper, the analog/mixed-signal performance is evaluated at device and circuit levels for a III-V nanowire tunnel field effect transistor (TFET) technology platform and compared against the predictive model for FinFETs at the 10-nm technology node. The advantages and limits of TFETs over their FinFET counterparts are discussed in detail, considering the main analog figures of merits, as well as the implementation of low-voltage track and-hold (T/H) and comparator circuits. It is found that the higher output resistance offered by TFET-based designs allows achieving significantly higher intrinsic voltage gain and higher maximum-oscillation frequency at low current levels. TFET-based T/H circuits have better accuracy and better hold performance by using the dummy switch solution for the mitigation of the charge injection. Among the comparator circuits, the TFET-based conventional dynamic architecture exhibits the best performance while keeping lower area occupation with respect to the more complex double-tail circuits. Moreover, it outperforms all the FinFET counterparts over a wide range of supply voltage when considering low values of the common-mode voltage

Observation of single phonon-mediated quantum transport in a silicon single-electron CMOS transistor by RMS noise analysis

We explore phonon-mediated quantum transport through electronic noise characterization of a commercial CMOS transistor. The device behaves as a single electron transistor thanks to a single impurity atom in the channel. A low noise cryogenic CMOS transimpedance amplifier is exploited to perform low-frequency noise characterization down to the single electron, single donor and single phonon regime simultaneously, not otherwise visible through standard stability diagrams. Single electron tunneling as well as phonon-mediated features emerges in rms-noise measurements. Phonons are emitted at high frequency by generation-recombination phenomena by the impurity atom. The phonon decay is correlated to a Lorentzian $1/f^2$ noise at low frequency.Comment: 5 pages, 3 figures, submitted to AP

Time Domain Analog Neuromorphic Engine Based on High-Density Non-Volatile Memory in Single-Poly CMOS

Increasing the energy efficiency of deep learning systems is critical for improving the cognitive capability of edge devices, often battery operated, as well as for data centers, constrained by the total power envelope. Specialized architectures accelerated by analog vector-matrix multipliers (VMMs) can reduce by orders of magnitude the energy per operation, since the reduced precision of analog computation does not undermine the classification accuracy of the neural network. We show an analog vector-matrix multiplier fabricated with industry-standard 0.18 μm CMOS process, exploiting a single-transistor non-volatile analog memory cell and dedicated technology circuit co-design. The design is focused on implementation in neural networks performing offline training. The VMM performs the analog multiplication of a vector of inputs, encoded in the duration of time pulses, times a matrix of weights, encoded in the programmable currents of the memory cells. A 1.72 μm2 memory cell is realized with a single transistor with floating gate, which can be operated as a two-terminal analog memristive device with more than 64 programmable current levels and high Ihigh/Ilow ratio (> 10 3 ), tuned by the charge injected in the floating gate. A small-area charge amplifier is used to convert the multiply and accumulate operation result into a voltage. System-level projections based on our measurements and simulations provide a throughput of 333.17 GOps/s and an energy efficiency of 122.3 TOps/J, higher than comparable-precision VMMs reported in the literature, and an equivalent area per cell down to 2.15 μm2 , lower than any similar state-of-the-art solution. Of critical importance in view of translation to industry, our proposal uses in a new way an industry-standard low-cost single-poly CMOS process flow

Design of Ultra-Low Voltage/Power Circuits and Systems

Over the last years, the Internet of Things (IoT), wireless sensor networks and the emergence of other energy-constrained applications have pushed the demand for low-cost systems-on-chip solutions, entailing tight area and small power/voltage budgets [...

Design of Ultra-Low Voltage/Power Circuits and Systems

Over the last years, the Internet of Things (IoT), wireless sensor networks and the emergence of other energy-constrained applications have pushed the demand for low-cost systems-on-chip solutions, entailing tight area and small power/voltage budgets [...